Senior Engineer Power Design Strategy: How to Avoid Conducting EMI Problems

Most conducted EMI problems are caused by common mode noise. Moreover, most common mode noise problems are caused by parasitic capacitance in the power supply.

We focus on what happens when parasitic capacitance is directly coupled to the power input wires.

1. A stray capacitance of just a few fF will cause the EMI scan to fail. Essentially, switching power supplies have nodes that provide high dV/dt. The mixing of parasitic capacitance with high dV/dt creates EMI problems. When the other end of the parasitic capacitor is connected to the power input, a small amount of current is pumped directly to the power line.

2. Look at the parasitic capacitance in the power supply. We all remember in the physics class that the capacitance between two conductors is proportional to the surface area of ​​the conductor and inversely proportional to the distance between the two. Look at each node in the circuit and pay special attention to nodes with high dV/dt. Think about the surface area of ​​the node in the circuit layout and how far the node is from the input line of the board. The drain and snubber circuits of the switching MOSFET are common culprit.

3. There are tricks to reduce the surface area. Try to use a surface mount package whenever possible. FETs in the upright TO-220 package have an extremely large drain tab surface area, but unfortunately it usually happens to be the node with the highest dV/dt. Try replacing it with a surface mount DPAK or D2PAK FET. By placing a primary ground plane on the low-level PCB under the DPAK tab, the bottom of the FET is well shielded, significantly reducing parasitic capacitance.

Sometimes the surface area needs to be used for heat dissipation. If you must use a TO-220 type FET with a heat sink, try connecting the heat sink to the primary ground (instead of grounding). This not only helps to shield the FET, but it also helps to reduce stray capacitance.

4. Let the switch node and the input connection pull apart. See the design example in Figure 1, where I ignored this simple principle.

Figure 1. Getting the input wiring too close to a node with a high dV/dt increases the conducted EMI.

I reduced the noise by about 6dB by simply adjusting the board (no circuit changes). See the measurement results in Figures 2 and 3. In some cases, close to high dV/dt for input line wiring can even damage common mode coils (CMC).

Figure 2. EMI scan from board layout where the AC input is closer to the switch circuit

Figure 3. EMI scan from board layout where the distance between the AC input and the switch circuit is large

Have you ever experienced this EMI improvement with little or no improvement after significantly enhancing the input filter? This is most likely because some stray capacitance from a high dV/dt node is directly coupled to the input line, effectively bypassing your CMC. To detect this, temporarily short the windings of the CMC on the PCB and connect a secondary CMC in series with the input wires of the board. If there is a significant improvement, you will need to re-layout the board and pay special attention to the layout and routing of the input connections.

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