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Abstract: MSM9841 is a large-scale integrated chip for mono/stereo voice control processing developed by OKI Electric Semiconductor Co., Ltd. of Japan. The structure, characteristics, working principle of the chip and its application in digital voice recorders are introduced.
Keywords: VCR MSM9841 FIFO
The MSM9841 is a mono/stereo voice control processing large-scale integrated chip with 1kbit FIFO (First In First Out) memory developed by OKI Electric Semiconductor of Japan. It can be easily interfaced with external systems or non-semiconductor memories and has multiple recording and playback modes. Because the chip uses the newer ADPCM2 algorithm, it can guarantee very high voice playback quality. The recording and playback functions of the MSM9841 can be controlled by the microprocessor via an 8/16-bit bus interface. The MSM9841 is available in a 56-pin QFP package with a supply voltage of 2.7V to 5.5V and an analog frequency of 4.096MHz with the following values: 4.0 kHz, 6.4 kHz, 8.0 kHz, 12.8 kHz, 16.0 kHz, 32.0 kHz. (Playback only); when the oscillation frequency is 5.6448 MHz, the sampling frequency can be selected from 22.05 kHz or 44.1 kHz (for playback only). The MSM9841 features an 8/16-bit bus interface and DMA interface and includes a low-pass filter, 14-bit A/D and D/A converter with a sampling frequency of 16 kHz or lower; a user-defined (256/512/1024-bit) FIFO Storage function (when using 8 kHz sampling frequency, 4bit ADPCM2/ADPCM algorithm, non-stereo mode, its buffer time is 32ms); supports 4 kinds of recording and playback compression algorithms, namely 4/5/6/7/8bit ADPCM2 algorithm, 4bit ADPCM algorithm , 16 bit PCM algorithm and 8bit nonlinear PCM algorithm; 8 levels of volume control (0dB ~ 21dB) can be realized by control commands.
2 pin arrangement and function
The pinout of the MSM9841 is shown in Figure 1. The function of each pin is as follows:
D15~D8: For 8-bit bus interface, these pins can be defined to the input/output interface of the external memory by commands. Otherwise, these pins can only be defined as input pins. For 16-bit bus interfaces, these pins can be used as a bidirectional data bus for external memory or microprocessors.
D7~D0: Bidirectional data bus to external memory or microprocessor.
WR: Write permission, low effective.
RD: Read allowed, low effective.
CS: The read/write function allows, low active (when low level, the read/write function is allowed to operate).
D/C: When this pin is high, voice data can be input or output from D0 to D15 pins. When this pin is low, the D0 to D7 pins are used to input control commands or output states.
BUSY: This pin outputs a low level when in recording, playback, and pause states.
Â Â Â EMP: When there is no data in the FIFO memory, the pin outputs a high level, and the pin can be changed from a high level to a low level by a command.
MID: This pin outputs a high level when the data in the FIFO exceeds half of the FIFO memory space. During playback, speech synthesis begins when MID is high. The MID can be changed from high level to low level by commands. This pin provides a synchronization signal for the input/output of speech when the FIFO is not being used.
FUL/DREQR: This pin outputs a high level when the FIFO memory is full. During playback, this pin is high and no data can be written to the FIFO. The high level of the FUL/DREQR output can be changed to a low level by the command input. When DMA conversion and stereo playback are selected, DREQR outputs a high level signal indicating that a DMA conversion is required. The high level of the DREQR output can also be changed to a low level by the command input.
CH/DACKR: When stereo playback is selected and CH is high, the EMP, MID or FUL pin outputs the status of the right shift FIFO. When CH is low, the EMP, MID, or FUL pin outputs the state of the left shift FIFO. This pin needs to be set low during recording and mono playback. This pin is DACKR when DMA conversion and stereo playback are selected. In this case, the DMA conversion response signal is input to DACKR. When DACKR is low, the IOW signal is accepted. The low level of the DACKR output can be changed to a high level by the command input.
DREQL: When DMA conversion and stereo playback are selected, a high level of DREQL output indicates that a DMA conversion is required. The high level of the DREQL output can be changed to a low level by the command input.
DACKL: When the DMA controller allows DMA conversion, a signal can be input to the DACKL terminal. If DACKL is low, the IOW and IOR signals will be accepted. When stereo playback is selected, the DMA conversion response signal of the left shift FIFO can be input to the DACKL terminal. The low level of the DACKL terminal can be changed to a high level by the command input. If you are not using DMA conversion, set this pin high.
IOW: This pin writes external data to the write pulse input pin of the MSM9841 during DMA conversion. Set this pin high if no DMA conversion is used.
IOR: This pin can be used as a read pulse input pin for the MSM9841 during DMA conversion. If you are not using DMA conversion, set this pin high.
Â Â Â ADSD: When using an external ADC, this pin is a 16-bit serial data input pin. If an external ADC is not used, this pin should be driven low.
DASD: When using an external DAC, this pin is a 16-bit serial data output pin.
SIOCK: When using an external ADC or DAC, this pin is a synchronous clock pin for 16-bit serial data input/output.
XT, XT: External oscillator connection pin, when an external clock is used, an external clock can be input to this pin.
VCK: Output sampling frequency for recording and playback. When an external ADC or DAC is used, the signal of the VCK pin is used as the sync signal.
RESET: Reset pin, active low.
TESTO, TESTI: Test pin, set this pin low.
SG: Analog ground output pin.
MIN, LIN: The inverting input of the internal OP amplifier, the internal input of the non-inverting input is connected to the signal ground.
MOUT, LOUT: MOUT is the output of the internal amplifier to MIN, and LOUT is the output of the internal amplifier to LIN.
AOUTL: Internal LPF (Low Pass Filter) left analog signal output. It is the playback signal waveform output that connects the pin to the amplifier to drive the speaker.
AOUTR: Internal LPF (Low Pass Filter) right analog signal output. It is the playback signal waveform output that connects the pin to the amplifier to drive the speaker.
DVDD: Digital power supply. A 0.1Î¼F capacitor should be connected between this pin and the digital ground.
DGND, AGND: Digital ground and analog ground.
AVDD: Analog power supply. A 0.1Î¼F capacitor should be connected between this pin and the analog ground.
3 internal structure and working principle
The internal structure of the MSM9841 is shown in Figure 2. It is mainly composed of microprocessor, timing controller, volume controller, ADPCM2/ADPCM/PCM analyzer, ADPCM2/ADPCM/PCM/nonlinear PCM synthesizer, direct memory access interface, FIFO, ADC, DAC, LPF and other components.
The MSM9841 can be controlled by binary encoding commands to complete recording, playback, stop, pause, volume adjustment, DMA conversion, setting internal or external D/A, A/D, signal output mode selection and other functions. The length of this control command is 8 bits.
4 Recorder with MSM9841 as the core
The recorder and recorder circuit based on MSM9841 is shown in Figure 3. The recorder and recorder adopts dual CPU mode, and the single-chip AT89C52 is used as the main control unit of the recording and playback module. The keyboard and liquid crystal display module use AT89C2051 as the main control unit to change commands and data through the serial port and the recording and playback module. Since the DRAM mode is not used in this recorder, the DMA control pins of the MSM9841 are connected to a high level. The level of the D/C pin in the MSM9841 determines the type of data on the data bus. When D/C is low, the signal on the data bus is the system control command; when D/C is high, the signal on the bus is voice data. Since the AT89C52 is an 8-bit microcontroller, and the MSM9841 supports a 16-bit or 8-bit data bus, when the system is working, it must first be set to the 8-bit data bus mode using the MSM9841 control command.
The audio output of the VCR uses the audio power amplifier LM386, and its circuit connection is shown in Figure 4. When the power supply voltage is +5V, the LM386 output power is about 300mW. The MSM9841 has two internal operational amplifiers that can be used to amplify the microphone's speech signal. Each op amp provides an inverting input and output, while the co-input is connected to the analog ground inside the chip. Two op amps can be cascaded to achieve the desired amplification by adjusting the external resistor value. The VLO can be adjusted by the following equation to be within the voltage range allowed by the LOUT pin:
When the supply voltage is 5V, the LOUT pin allows a voltage range of 1 to 4V. The LOUT pin is connected to the input low-pass filter inside the chip and can be used to remove input frequency components exceeding 1/2 of the sampling frequency. In this way, the Nyquist theorem applicable to the data sampling system can be satisfied, and then the ADC is sent for data sampling. The amplifying circuit is connected to the microphone through a DC blocking capacitor, and the DC blocking capacitor is mainly used to remove the DC signal in the low-level AC signal (about 2 to 20 mV). The entire audio input circuit is shown in Figure 5.
The entire recorder system uses four 2M Ã— 8 bit DRAM MSM5116800 as the voice storage medium. At the higher quality 8kbps sampling rate, if the 4-bit ADPCM2 algorithm is used, the 4 MSM5116800 can record a voice length of about 4Ã—. 1.024 Ã— 2000 Ã— 8 / (8 Ã— 4) = 2048s. The address bus of the 2MÃ—8 bit DRAM has a total of 20 bits, which are divided into a high-order address (that is, A0 to A8 and A9R to A11R have 12 bits to form a row address) and a lower address (that is, a column address composed of 9 bits of A0 to A8). Column address), the two share the 9 address lines A0 ~ A8 by time division multiplexing, the addressing range of each DRAM is 000000H ~ 7FFFFFH, each chip DRAM is distinguished by different CAS signal lines. DRAM has a variety of different read and write modes and memory cell data refresh mode. In this system, since the required data rate is very low, the most basic read and write mode can be used, that is, the complete address signal is sent first (including the line). The address and column address are then read and written; the refresh mode uses the cas-before-ras method and interpolates the refresh pulse to the middle of the read and write timing.
The system completes the operation of recording and playback by receiving keyboard commands. When recording, first use the binary command to initialize the MSM9841. The specific content includes: setting the speech synthesis mode to 4 bit ADPCM2 algorithm; selecting to use internal ADC; setting the bus width to 8 bits; not using DMA mode; configuring FIFO size, FIFO The maximum configurable is 1024 bit; set the mode of output data; set the sampling frequency to 8.0 kHz. This sampling frequency makes the voice quality much better than the phone's sound quality. Increasing the sampling frequency also further improves the sound quality, but the recording time is shortened accordingly; conversely, a lower sampling frequency increases the recording time but reduces the sound quality.
Â Â Â After the initialization is completed, the control command 10H (sampling frequency is 8.0 kHz) can be issued to start the recording operation. During the recording process, when the voice data in the FIFO exceeds half of the FIFO memory space, the MID pin will go high and an external interrupt signal will be sent to the INT1 end of the MCU (microprocessor) to cause the MCU to generate an interrupt response. At this time, the MCU starts to read the voice data in the FIFO, and then transfers it to the DRAM. During the reading process, the state of the EMP terminal is also checked to avoid the FIFO reading.
As with the recording, the same initialization is performed first during playback, and then the control command 20H (sampling frequency is 8.0 kHz) is used to initiate the playback operation. The MCU starts to read the voice data to be played from the DRAM and writes it into the FIFO. When the voice data in the FIFO is full, the FUL pin will go high and an external interrupt signal is sent to the INTO end of the MCU. To cause the MCU to generate an interrupt response, stop writing data to the FIFO at this time.
During the recording and playback of the MCU, a pause or stop command can be issued to the MSM9841 according to the keyboard command to pause or end the recording and playback operations. At the same time, the liquid crystal display is used to display the currently performing operations and operation results. Through the keyboard and LCD for human-machine communication, it is convenient to realize multi-segment voice recording and playback operations and volume adjustment functions.
The MSM9841-based VCR has a recording and playback time of approximately 34 minutes when using a bit rate of 8kbps. If you need to extend the recording and playback time, you can expand the storage section. The system uses inexpensive DRAM as a voice storage medium and is therefore less expensive. The whole machine has a series of advantages such as simple structure, reliable performance, friendly human-machine interface and convenient use, so it has a good application prospect. If the storage part of the DRAM is replaced by FLASH or ferroelectric memory, the machine can also be widely used in bus reporting system, recording telephone, automatic voice service desk and other fields.
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