Abstract: This article is the realization scheme of multi-chip digital signal processing system based on ADSP-TS101S. The system is applied to a radar signal processor. The article first introduces the composition of the signal processing system composed of multiple TIgerSHARC DSP chips; secondly estimates the amount of operation of the system and the required calculation time; and finally specifies the method for the CPLD to generate the reset signal and implement the parallel-serial conversion function.
Introduction With the continuous improvement of real-time signal processing requirements and the rapid development of large-scale integrated circuits, DSP, which is the core and symbol of digital signal processing, has been rapidly developed and applied. This article is based on a DSP from Analog Devices-TIgerSHARC, which introduces a set of specific implementation schemes in the signal processing system in more detail.
Figure 1 Block diagram of signal processor
System design and function introduction of each part This system is the signal processor of a certain radar, reads the intermediate frequency data through ADC, DSP1, DSP2 complete the pulse compression and side lobe suppression of the data, DSP3, DSP4 complete the data accumulation and modulus, DSP5 realizes Normalization of video data, output of video data through DAC and transmission of parallel data. The system structure is shown in Figure 1.
In this system, ADC adopts AD9225 with 12 effective data bits and 25MSPS conversion rate to convert the two analog signals of I and Q into digital signals at a certain sampling rate, and the high 10 bits are sent to DSP.
This system uses TIgerSHARC DSP. The chip has a maximum operating speed of 300MHz and a core instruction cycle of 3.3ns. It can execute up to 4 instructions per cycle, 24 16-bit fixed-point operations and 6 floating-point operations, and contains 6MB of on-chip SRAM It has high storage and computing performance, and has high application value in the field of signal processing. In order to simplify the system hardware and reduce the connection between DSP chips, the five DSPs of the system are connected in a loosely coupled link. DSP1 reads in the I and Q data after demodulation of the intermediate frequency through external DMA. DSP1 performs pulse compression (matching filtering) on ​​the part of the read data, and sends the processed data and unprocessed data to the link port 2 to DSP2. DSP2 performs pulse compression on the remaining data. DSP2 sends all processed data to DSP3. Due to the accumulation of dozens of frames, the amount of data is very large, DSP3 and DSP4 respectively undertake half of the data accumulation, modulo operation. DSP4 sends the modulo result to DSP5. DSP5 normalizes the data to generate video data, and the video data is sent out through the external port in DMA mode. In different working modes, parallel data is also sent to the CPLD.
Program loading: This system adopts EPROM program boot mode. When using the link port of TIgerSHARC DSP for data transmission, the length of each sent word must be set to 4 words, the number of sent words must be a multiple of 4, and the data start address must be aligned every 4 words. Therefore, the sending DSP must read 4 32-bit words from the EPROM every time and send them through the load link.
The DAC uses a high-speed device AD9750 with 10-bit effective data bits and a conversion rate of 125 MSPS to convert video data to an analog signal at a fixed rate.
Figure 2 Block diagram of pulse compression filter algorithm
Figure 3 TigerSHARC DSP power-on reset waveform
CPLD completes functions such as data latching, DSP reset signal generation, and serial data output that converts parallel data to a certain baud rate (serial output meets the RS-232 standard).
Clock: The clock generated by the 40MHz crystal oscillator in the board is used inside the DSP. The A / D sampling clock should be phase-locked with the system clock, so the 10MHz system clock is phase-locked to 40MHz through the ICS 601M, and the CPLD is input through the 40ME pin. The A / D sampling clock signal is generated after frequency division. Produced by it. The single board can only work with the on-board clock when debugging, so the 40ME should be selected with a jumper.
Power supply: TigerSHARC DSP has three power supplies, digital 3.3V for I / O power supply; digital 1.2V for DSP core power supply; analog 1.2V for internal phase-locked loop and frequency multiplier circuit power supply. TigerSHARC DSP requires digital 3.3V and 1.2V to be powered on at the same time. If strict synchronization is not possible, ensure that the core power supply is 1.2V and the I / O power supply is 3.3V. This system connects a large capacitor at the digital 3.3V input terminal and a small capacitor at the digital 1.2V input terminal, making the 3.3V charging time greater than the 1.2V charging time, which solves the problem of power supply sequencing. Each digital 1.2 V power supply of each DSP is supplied by a MAX1951 which converts + 5V to 1.2V. The analog 1.2V power supply of all DSPs is unified by a piece of REG1117A to convert analog + 5V to 1.2V supply. The I / O 3.3V power supply of 5 DSPs is supplied by a REG1117 to convert digital + 5V to 3.3V.
System calculation analysis and calculation time estimation According to the task of signal radar processing, the calculation amount of each component of the system is specifically analyzed below to estimate the calculation time required. (Signal processing should be less than 1ms per frame)
Pulse compression uses FFT technology to achieve pulse compression filtering, the algorithm is shown in Figure 2. According to the operation needs, 512, 1024 and 4096 point complex FFT are to be done. After the complex FFT is completed, it must be multiplied by the pre-stored matched filter coefficients H (k). 512, 1024, and 4096 complex multiplications are required, and the result of the multiplication must be 512, 1024, and 4096 complex IFFT to obtain Pulse pressure result. TS101 does 1024 point complex FFT (IFFT) in the actual application of this system takes about 50ms (working at 200MHz). It can make full use of the characteristics of TS101 dual operation block, single instruction multiple data (SIMD), and perform complex multiplication of two distance units at the same time. It takes only 15ms to complete 1024 complex multiplications. This completes 512, 1024, and 4096 pulse compression, which requires 60ms, 120ms, and 460ms, respectively. Because DSP1 needs to use DMA to read each frame of data in segments, there is not enough time to perform 4096-point pulse compression, so it is completed in DSP2.
Sidelobe suppression Use side-domain synthesis method to perform sidelobe suppression on the bi-phase code, and integrate the sidelobe suppression coefficients in the pulse compression matched filter coefficients to achieve the effect of suppressing sidelobes. The algorithm is implemented on the basis of pulse compression, and has no additional effect on the amount of DSP calculation and time.
Accumulation Accumulation uses the sliding window accumulation method, which requires less calculation, and TS101 has a greater time surplus. The actual requirement is at least 35 frames accumulation. Each cycle of I and Q has a total of 2 × 3200 points, and requires about 2 × 3200 × 35 = 224K bytes of storage space. Therefore, the accumulation operation is completed in DSP3 and DSP4 respectively.
CPLD generates reset signal and realizes parallel-serial conversion function Reset signal generation
The power-on reset type of TigerSHARC DSP is special, and it should be fully paid attention to in the design. This system uses Altera's CPLD EPM7192 to generate the power-on reset waveform and timing control. The power-on reset waveform requirements are shown in Figure 3.
It should be noted here:
tstart_LO must be greater than 1ms after the power supply is stable;
tpulse1_HI must be greater than 50 system clock cycles and less than 100 system clock cycles;
tpulse2_LO must be greater than 100 system clock cycles.
Normal reset after DSP power-on: The low-level duration must be greater than 100 system clock cycles.
Realization of parallel-serial conversion function Parallel data is sent from DSP to CPLD, which is converted into serial data by CPLD and sent at a fixed baud rate. The program written in AHDL language supported by MAX + plusII has realized the parallel-to-serial conversion function, which has the advantages of flexibility, simplicity and strong scalability. The specific procedures will not be repeated.
Conclusion The implementation of the multi-chip TigerSHARC DSP in real-time signal processing system introduced in this paper has been successfully applied to the improvement of a radar signal processor. Structurally, the original three circuit boards are combined into one; the number of chips is reduced from the original (ADSP21062) dozens to five (ADSP TS101S). On the basis of completing the original functions, some functions to improve performance are also realized. And the power consumption of the new system is greatly reduced compared to the original, and the heat dissipation is also significantly reduced. Practice shows that the system hardware structure composed of TigerSHARC DSP is simple, the software is easy to write, and the cost is low, which has high engineering application value.
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