How to grow into a qualified FPGA developer

Many friends in the forum just entered the EDA design field. Since entering this forum, many friends have talked about their expectations and confusion. Below I just talk about some of my personal thoughts and hope to help you a little. Also welcome more friends to participate in the discussion and express your opinions!
When I first entered this line, I was fortunate enough to participate in a very large project in a large company, which was greatly benefited by the guidance of many seniors. In retrospect, it can be regarded as a lot of emotions. I will share my experience of detours and summed up experience with you. I hope to have a little reference value for you.

Start by talking about how to be a qualified designer. Beginners feel that everything is a challenge, everything is fresh, I don't know where to start. I have summarized the 4 steps to learn EDA logic design, please take a brick!
1. First of all, you should study the design and design process of FPGA/CPLD.
Don't simply think that design input - "simulation -" comprehensive - "to achieve such a thing, to be fine, to learn fine, to ask more attention to each step, to distinguish the relevant steps and differences. For example, to understand the function simulation, integrated simulation, Translate simulation, Map simulation, layout and post-mortem simulation, what time should be done, when can not do these simulations! Learning to understand the biggest benefit of the design process is to help develop good EDA design habits, and will benefit in the future!
2. About design input and Coding Style.
Design input is best to learn HDL language, Verilog, VHDL can be, you can add state machine input and schematic input as a supplement, but not the point. I have repeatedly emphasized the importance of Coding Style in the previous post. Because it is a basic business quality of logic designers. Moreover, Coding Style is not a few articles. If you learn a few principles, you can become a master. He needs you to constantly experience and accumulate at work. At the beginning of the study, there is a sense of Coding Style, and the designer will intentionally accumulate. It is good for future development. On the contrary, there will be endless troubles.
3. Cultivate the awareness of hardware and cultivate the concept of the system.
I also emphasize hardware awareness when communicating and teaching. If we look at the form, logical design will become more flexible and simpler with the continuous development of intelligence and optimization methods. For example, when we are using a large FPGA, we rarely talk about how to use Floorplanner optimization, manual routing, if you use manual mode, its workload is too big! The key to a design depends on its designer's hardware awareness and system awareness. Hardware awareness requires that the hardware of the design be well-informed first. The HDL code is just a tool for expressing the hardware in mind. System awareness requires designers to have a macro concept, and have a suitable arrangement for the design of the global, such as clock domain, module reuse, constraints, area, speed and other issues. Be aware that the area saved by the multiplex module on the system is much more affordable than the small amount of code on the code.
4. Finally, the use of tool software.
Now EDA software is getting more and more friendly and more and more "stupid". If you haven't used the software for a year, I dare say that it is a bad software (at least on the user interface). Because this is contrary to the concept of EDA. But as a designer, software is a tool, you should be proficient in different aspects of the software, so that you can maximize your ingenuity, in order to make you even more powerful!

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