Phenomenon 1: The PCB design requirements of this board are not high, just use a thin line and automatically cloth it.
Comments: Automated wiring must occupy a larger PCB area, and at the same time produce more than a lot of vias than manual wiring. In large batches of products, the factors considered by PCB manufacturers to cut prices are line width and The number of holes, which affect the yield of the PCB and the consumption of the drill bit, respectively, saves the cost of the supplier, and finds a reason for the price reduction.
Phenomenon 2: These bus signals are pulled with a resistor, and I feel relieved.
Comments: There are many reasons why the signal needs to be pulled up, but not all of them have to be pulled. The pull-down resistor pulls a simple input signal, and the current is tens of microamps or less. However, if a signal is driven, the current will reach milliamperes. The current system is usually 32 bits of address data, and there may be After the 244/245 isolated bus and other signals are pulled up, a few watts of power is consumed by these resistors.
Phenomenon 3: How to deal with these unused I/O ports of CPU and FPGA? Let it be empty first, and then talk about it later.
Comments: If the unused I/O port is left floating, it may become an input signal of repeated oscillations due to a little interference from the outside world, and the power consumption of the MOS device basically depends on the number of times the gate circuit is flipped. If you pull it up, each pin will also have a micro-ampere current, so the best way is to set it as an output (of course, you can't connect other driven signals outside)
Phenomenon 4: There are so many doors left in this FPGA, so let's play it out.
Comments: The power consumption of FGPA is proportional to the number of flip-flops used and the number of flips, so the power consumption of the same model FPGA at different times of different circuits may differ by a factor of 100. Minimizing the number of flip-flops at high speeds is the fundamental way to reduce FPGA power consumption.
Phenomenon 5: The power consumption of these small chips is very low, no need to consider
Comments: It is difficult to determine the power consumption of the chip that is not too complicated inside. It is mainly determined by the current on the pin. An ABT16244 consumes less than 1 mA without load, but its indicator is each foot. Can drive 60 mA load (such as matching tens of ohms of resistance), that is, the maximum power consumption of up to 60 * 16 = 960mA, of course, only the power supply current is so large, the heat is falling on the load.
Phenomenon 6: The memory has so many control signals. I only need to use OE and WE signals on this board. The chip selection is grounded, so the data is much faster when reading.
Comments: Most of the memory power consumption is more than 100 times larger than when the chip select is valid (regardless of OE and WE), so CS should be used to control the chip as much as possible, and if other requirements are met, It is possible to shorten the width of the chip select pulse.
Phenomenon 7: How do these signals have overshoot? As long as the match is good, it can be eliminated.
Comments: Except for a few specific signals (such as 100BASE-T, CML), there are overshoots. As long as they are not very large, they do not necessarily need to match, even if the match is not the best match. The output impedance of TTL is less than 50 ohms, and some even 20 ohms. If such a large matching resistor is used, the current is very large, the power consumption is unacceptable, and the signal amplitude will be too small to be used. In addition, the output impedance of the general signal at the output high level and the output low level is not the same, and there is no way to achieve a perfect match. Therefore, the matching of signals such as TTL, LVDS, and 422 can be accepted as long as the overshoot is acceptable.
Phenomenon 8: Reducing power consumption is a matter for hardware personnel, and it has nothing to do with software.
Comments: The hardware is just a stage. The software is the software. The access of almost every chip on the bus and the flipping of each signal are almost controlled by software. If the software can reduce the number of external accesses (use more register variables, More use of internal CACHE, etc., timely response to interrupts (interrupts are often active low with pull-up resistors) and other specific measures for specific boards will greatly contribute to reducing power consumption.
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