introduction
With the development of multimedia and network technology, the characteristics of digital image with large information volume are more and more demanding on image compression technology. Therefore, dedicated high-speed digital information processing technology has become the development direction. TI's C5000 series of DSPs will bring the focus of signal processing systems back to software algorithms. In the research of compression algorithms, many algorithms such as DCT and wavelet are more and more popular because of their high reliability and high efficiency.
System hardware design
Feasibility analysis of TMS320C5409 as the main processor
The TMS320C5409 has a clock frequency of 100MHz and is extremely cost effective. Using an improved Harvard architecture built around a set of program buses, three data buses, and four sets of address buses, the addressing and readings can be performed simultaneously. There are independent hardware multipliers, which are beneficial to implement a large number of repeated multiplication operations in algorithms such as optimized convolution, digital filtering, FFT, and matrix operations. It has special instructions such as cyclic addressing and bit reversal. These instructions greatly improve the addressing, sorting and calculation speed in FFT and convolution operations. There are one or more sets of independent DMA buses working in parallel with the CPU program and data bus.
In this system, the TMS320C5409 acts as the main processor and the task is to implement JPEG compression encoding.
It is not difficult to obtain by analysis. When processing an image with a frame size of 640 & TImes; 480, the time required for JPEG compression coding is: T = 62 & TImes; 10 (ns) & TImes; 640 × 480 = 0.119866s, when the processed image With a lower resolution, it takes less time to compress each frame, which is completely feasible for applications where real-time requirements are not very high.
Hardware design block diagram
FIG. 1 is a structural diagram of an image processing system based on TMS320C5409. C5409 is the central processing unit, SRAM is the DSP off-chip extended data memory, EEPROM is the program memory when working offline, it is used to store the boot program of the system and other applications, and the A/D conversion part is responsible for converting the image into digital signal. Stored in frame memory. The address decoding and image acquisition system control circuit generates the address decoding signals of each part of the system, maps them to different address areas, and controls the ADC for image acquisition, which is controlled by the CPLD; the register control of the image acquisition chip is 51. The microcontroller is completed.
Storage space expansion plan
The A/D converted raw image data is very large. The TMS320C5409 has only 32KB of RAM and 16KB of ROM inside, which is not enough. Therefore, the memory must be expanded to store the original image data and applications. This article considers external 64KB of RAM and 512KB of Flash, RAM uses Cypress's CY7C1021V33, and Flash uses SST's SST39VF512. Since the data space of the C5409 is only 64KB, the memory page expansion technology is adopted. The extended output ports 1Q and 2Q of the C5409 serve as page selection signals for the extended memory. Use the A15 pin and XF pin of C5409 to control the generation of the extended memory chip select signal through the 3/8 decoder. When A15=0, select the on-chip RAM; when A15=1, XF=0 select the off-chip. SRAM; when A15=1, XF=1, select off-chip flash; the expansion of memory is shown in Figure 2. 48 KB of the 64 KB of the external expansion RAM is used to store the original image data, and 16 KB is used to store the compressed image and program and the temporarily stored data.
DSP chip power circuit design
The main issues to consider in power supply design are power and heat dissipation. Power requirements: The current consumption depends mainly on the activation of the device, that is, the activation degree of the CPU. The peripheral power consumption mainly depends on the peripherals that are working and their speed. Compared with the CPU, the peripheral power consumption is relatively small. Taking the TMS320C5409 as an example, when the FFT operation is performed, the required power supply current is the largest. Therefore, when designing the power supply, it must be considered to leave a certain margin between the power supply current and the actual required current, because the peak current will be larger and the margin is at least 20%.
The C5409 uses a dual power supply mechanism with operating voltages of 3.3V and 1.8V. Among them, 1.8V mainly provides voltage for the internal logic of DSP, including CPU and all other peripheral logic. The external interface pins are powered by 3.3V. The system's power supply uses TI's two-output power chip TPS73HD318, which is a dual output regulator. The output voltage is 3.3V for one channel and 1.8V for one channel. The maximum output current of each power supply is 750mA.
JPEG image compression algorithm
JPEG algorithm optimization
Although the JPEG basic system is capable of low compression ratio compression of images, DCT and IDCT are the most time-consuming operations in the software implementation process, and since the spectral characteristics of the image itself are not considered, the JPEG quantization table compresses all images and Not necessarily optimal. The fast DCT algorithm can improve the speed of the software and enhance the real-time performance of the software. At the same time, according to the spectral characteristics of the image itself, the quantization table recommended by JPEG is adaptively improved.
Fast DET algorithm
If you divide an image into a number of 8 × 8 small blocks and directly perform 2D-DCT conversion, the amount of calculation will be very large. Therefore, it is necessary to convert an 8×8 two-dimensional DCT transform into two 8-point one-dimensional DCT composite operations. The specific method is to perform DCT transformation in the column direction for each 8×8 block to obtain an intermediate matrix, and then perform DCT transformation on each row of the matrix. It can be seen that the 2×DCT of the 8×8 matrix can be converted into 16 one-dimensional 8-point DCTs.
At present, many DCT fast algorithms for one-dimensional DCT operations have been proposed. Among them, the Loeffler algorithm requires the least amount of calculation. The Loeffler algorithm divides the 8-point one-dimensional DCT operation into four levels. Due to the dependency of the input/output between the levels, the four-level operation must be performed serially, and the internal operations of each level can be processed in parallel.
There are three operational factors in the flow chart: the butterfly factor, the rotation factor, and the multiplication factor, as shown in a, b, and c in Figure 3, respectively. The operational relationship of the butterfly factor is:
D0=I0+I1
O1=I0-I1
It takes two additions to complete, and the input/output relationship of the multiplication factor is relatively simple: only one multiplication is required, and the operation relationship of the twiddle factor is:
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