When you need to output the signal inside the FPGA/CPLD to the external related device through the pin, if it does not affect the function, it is better to use these signals to be latched and output. Because usually a board works in one or two clock modes, the working clock of the chip connected to the FPGA/CPLD is in most cases the same as the clock of the FPGA. If the output signal is clocked, it can be used. To the following role:
Easy to meet the timing requirements of signal connections between chips;
Easy to meet the signal establishment and retention time;
As shown in the above figure, for example, FPGA/CPLD latches a signal on the clock edge 1 of CLK to get the waveform indicated by SIG. The SIG signal needs to be given to another chip with its interface, then the chip will be on the clock edge of CLK 2 The SIG signal is correctly sampled. However, if the signal is not latched with the clock edge when it is output in the FPGA/CPLD, there will be a timing relationship shown by SIG1/SIG2, and the chip with its interface will sample the signal at clock edge 2. There may be cases where the setup hold time does not meet the requirements and the sampling is unreliable, along the edge. In addition, there are cases where glitch may occur through the combined logic output. All of these non-standard designs can cause unreliable and unstable conditions when the system is working.2.5 Registered asynchronous input signal
In our daily design work, the FPGA/CPLD is always connected to other chips. The FPGA/CPLD will output signals to other chips, and also process the signals sent by other chips. These signals are often applied to the FPGA. /CPLD internal clock system is asynchronous, in order to reliably sample these input signals, it is recommended to use these input signals after the corresponding clock is latched and processed:
Converting the original asynchronous signal into synchronization for processing;
Remove glitches in the input signal (especially for the data bus);
Input and output latches for signals in FPGA/CPLD
2.6 Clock Design in FPGA/CPLD
Whether it is discrete logic, programmable logic, or any digital design implemented with fully custom silicon devices, a reliable clock is critical to successful operation. Poorly designed clocks can lead to erroneous behavior at extreme temperature, voltage or manufacturing process variations, and can be difficult to debug and costly. Several clock types are typically used when designing an FPGA/CPLD. The clock can be divided into the following four types: global clock, gated clock, multi-level logic clock, and wave clock. A multi-clock system can include any combination of the four clock types described above.
No matter which way, the real clock tree in the circuit can't reach the ideal clock. Therefore, we must build an actual working clock model to analyze the circuit according to the ideal clock, so that the actual working effect of the circuit is the same as expected. . In the actual clock model, we have to consider the skew, jump and absolute vertical deviations in the clock tree propagation and other uncertainties.
For the register, when the clock working edge comes, its data end should be stable, so as to ensure the correctness of the data sampled by the clock working edge. The preparation time of this data is called setup TIme. The data should also be held for a while after the clock working edge has elapsed. This time is called hold TIme. Therefore the specific clock is shown in Figure 5. The network delay refers to the propagation delay of the clock and the deviation of the jump due to the non-vertical equivalent. On this basis, some uncertain factors are considered. The actual working clock edge is as shown in the figure. The hold time and setup time are relative to the actual clock hopping. Therefore, these factors must be taken into consideration when determining the timing of the circuit, so that the setup time and the hold time meet the requirements.
Figure 5 working clock model
In order for the circuit to work properly, the setup and hold times should be met separately:
Where tclock_Q_max is the slowest change of the clock edge change to the data output, tlogic_max is the maximum possible delay of the combination logic between registers, tclock_Q_min and tlogic_min indicate the fastest case. When considering the establishment of the hold time, the clock tree should be considered to be skewed backwards. When considering the setup time, the clock tree should be considered to be skewed forward. In post-simulation, the maximum delay is used to check the settling time and the minimum delay is used to check the hold time.2.6.1 Global Clock
For a design project, the global clock (or synchronous clock) is the simplest and most predictable clock. The best clocking scheme in a PLD/FPGA design is a single master clock driven by a dedicated global clock input pin to clock each flip-flop in the design project. Whenever possible, try to use a global clock in your design project. PLD/FPGA has a dedicated global clock pin that connects directly to each register in the device. This global clock provides the shortest clock-to-output delay in the device.
Figure 1 shows an example of a global clock. The timing waveform of Figure 1 shows that the data input D[1..3] of the flip-flop should follow the constraints of setup time and hold time. The values â€‹â€‹for setup and hold times are given in the PLD data sheet and can also be calculated using the software's timing analyzer. If the setup and hold time requirements are not met in the application, the clock must be used to synchronize the input signal (see the next chapter "Asynchronous Inputs").
Figure 1 Global Clock
(The best way is to use the global clock pin to clock every register in the PLD, so the data only needs to follow the relative clock setup time tsu and hold time th)2.6.2 Gated Clock
tcl , https://www.tclgroupss.com